//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2013 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 149903
// File Date           :  2013-05-08 18:23:05 +0100 (Wed, 08 May 2013)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : HDL design file for AMBA interface block master domain
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                        nic400_ib_tpv_gp_apb4_ib_master_domain_ysyx_rv32.v
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//  Master domain of AMBA Interface Block (IB) 'tpv_gp_apb4_ib'.
//
//  This IB is a component of AMIB named tpv_gp_apb4
// 
//
//           SIF prot axi4
//           MIF prot itb
//           SIF DW   32
//           MIF DW   32
//
//           MIF  itb_m
//           RIF  itb_m
//           IIF  itb_m
//           BIF  itb_m
//
//           ID Width    = 4
//           drive_id    = false
//
//           Burstbrk    = false
//
//------------------------------------------------------------------------------


`include "nic400_ib_tpv_gp_apb4_ib_defs_ysyx_rv32.v"



module nic400_ib_tpv_gp_apb4_ib_master_domain_ysyx_rv32
  (
  
    //itb_m ITB bus

    //A Channel
    aid_itb_m,
    aaddr_itb_m,
    alen_itb_m,
    asize_itb_m,
    aburst_itb_m,
    alock_itb_m,
    acache_itb_m,
    aprot_itb_m,
    awrite_itb_m,
    avalid_itb_m,
    aregion_itb_m,
    aready_itb_m,

    //W Channel
    wdata_itb_m,
    wstrb_itb_m,
    wlast_itb_m,
    wvalid_itb_m,
    wready_itb_m,

    //D Channel
    did_itb_m,
    ddata_itb_m,
    dresp_itb_m,
    dlast_itb_m,
    dbnr_itb_m,
    dvalid_itb_m,
    dready_itb_m,

    //Inter-domain IB bus

    //A Inter-domain bus
    a_data_async,
    a_rpntr_gry_async,
    a_rpntr_bin,
    a_wpntr_gry_async,

    //D Inter-domain bus
    d_data_async,
    d_rpntr_gry_async,
    d_rpntr_bin,
    d_wpntr_gry_async,

    //W Inter-domain bus
    w_data_async,
    w_rpntr_gry_async,
    w_rpntr_bin,
    w_wpntr_gry_async,

    //Clock and reset signals
    aclk_m,
    aresetn_m

  );




  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //itb_m ITB bus


  //A Channel
  output  [3:0]       aid_itb_m;              //id of itb_m bus
  output  [31:0]      aaddr_itb_m;            //address of itb_m bus
  output  [7:0]       alen_itb_m;             //length field of itb_m bus
  output  [2:0]       asize_itb_m;            //size of itb_m bus
  output  [1:0]       aburst_itb_m;           //burst length of itb_m bus
  output              alock_itb_m;            //lock of itb_m bus
  output  [3:0]       acache_itb_m;           //cache field of itb_m bus
  output  [2:0]       aprot_itb_m;            //prot field of itb_m bus
  output              awrite_itb_m;           //direction of itb_m bus
  output              avalid_itb_m;           //valid of itb_m bus
  output  [3:0]       aregion_itb_m;          //region selection signal of itb_m bus
  input               aready_itb_m;           //ready of itb_m bus

  //W Channel
  output  [31:0]      wdata_itb_m;            //write data of itb_m AXI bus W Channel
  output  [3:0]       wstrb_itb_m;            //write strobes of itb_m AXI bus W Channel
  output              wlast_itb_m;            //write last of itb_m AXI bus W Channel
  output              wvalid_itb_m;           //write valid of itb_m AXI bus W Channel
  input               wready_itb_m;           //write ready of itb_m AXI bus W Channel

  //D Channel
  input   [3:0]       did_itb_m;              //id of itb_m bus
  input   [31:0]      ddata_itb_m;            //data of itb_m bus
  input   [1:0]       dresp_itb_m;            //response status of itb_m bus
  input               dlast_itb_m;            //last of itb_m bus
  input               dbnr_itb_m;             //response type of itb_m bus
  input               dvalid_itb_m;           //valid of itb_m bus
  output              dready_itb_m;           //ready of itb_m bus

  //Inter-domain IB bus


  //A Inter-domain bus
  input   [61:0]      a_data_async;           //A Channel Data
  output  [1:0]       a_rpntr_gry_async;      //A Channel Read Pointer (GRY)
  output              a_rpntr_bin;            //A Channel Read Pointer (BIN) for data mux
  input   [1:0]       a_wpntr_gry_async;      //A Channel Read Pointer (GRY)

  //D Inter-domain bus
  output  [39:0]      d_data_async;           //D Channel Data
  input   [1:0]       d_rpntr_gry_async;      //D Channel Read Pointer (GRY)
  input               d_rpntr_bin;            //D Channel Read Pointer (BIN) for data mux
  output  [1:0]       d_wpntr_gry_async;      //D Channel Read Pointer (GRY)

  //W Inter-domain bus
  input   [36:0]      w_data_async;           //W Channel Data
  output  [1:0]       w_rpntr_gry_async;      //W Channel Read Pointer (GRY)
  output              w_rpntr_bin;            //W Channel Read Pointer (BIN) for data mux
  input   [1:0]       w_wpntr_gry_async;      //W Channel Read Pointer (GRY)

  //Clock and reset signals
  input               aclk_m;           
  input               aresetn_m;        


  // ---------------------------------------------------------------------------
  // Internal signals
  // ---------------------------------------------------------------------------

  // A Channel wires at boundary
  // PLoad width 62
  
  wire                a_boundary_dst_valid;
  wire                a_boundary_dst_ready;

  wire [61:0]         a_boundary_dst_data;     // concatenation of the registered inputs


  // D Channel wires at boundary
  // PLoad width 40
  
  wire                d_boundary_src_valid;
  wire                d_boundary_src_ready;

  wire [39:0]         d_boundary_src_data;     // concatenation of the inputs
  wire [39:0]         d_boundary_dst_data;     // concatenation of the registered inputs


  // W Channel wires at boundary
  // PLoad width 37
  
  wire                w_boundary_dst_valid;
  wire                w_boundary_dst_ready;

  wire [36:0]         w_boundary_dst_data;     // concatenation of the registered inputs


  wire [1:0]          a_rpntr_gry_async;           // gray encoded rd-pointer for A channel
  wire                a_rpntr_bin;           // binary encoded pointer for read data mux
  wire [1:0]          a_wpntr_gry_async;           // gray encoded wr-pointer for full/empty calc

  wire [1:0]          w_rpntr_gry_async;           // gray encoded rd-pointer for w channel
  wire                w_rpntr_bin;           // binary encoded pointer for read data mux
  wire [1:0]          w_wpntr_gry_async;           // gray encoded wr-pointer for full/empty calc

  wire [1:0]          d_rpntr_gry_async;           // gray encoded rd-pointer for D channel
  wire                d_rpntr_bin;           // binary encoded pointer for read data mux
  wire [1:0]          d_wpntr_gry_async;           // gray encoded wr-pointer for full/empty calc

  // ITB_itb_m wires

  // A Channel
  wire                avalid_itb_m;
  wire                aready_itb_m;

  // D Channel
  wire                dbnr_itb_m;
  wire                dvalid_itb_m;
  wire                dlast_itb_m;
  wire [31:0]         ddata_itb_m;
  wire [1:0]          dresp_itb_m;
  wire [3:0]          did_itb_m;
  wire                dready_itb_m;

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------




  // ---------------------------------------------------------------------------
  // A Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the boundary outputs
  assign {
          aid_itb_m,
          awrite_itb_m,
          aaddr_itb_m[31:0],
          alen_itb_m,
          asize_itb_m,
          aburst_itb_m,
          alock_itb_m,
          acache_itb_m,
          aregion_itb_m,
          aprot_itb_m} = a_boundary_dst_data;

  

  assign avalid_itb_m = a_boundary_dst_valid;
  assign a_boundary_dst_ready = aready_itb_m;






  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the boundary outputs
  assign {
          wdata_itb_m,
          wstrb_itb_m,
          wlast_itb_m} = w_boundary_dst_data;

  

  assign wvalid_itb_m = w_boundary_dst_valid;
  assign w_boundary_dst_ready = wready_itb_m;




  // ---------------------------------------------------------------------------
  // D Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign d_boundary_src_data = {
          did_itb_m,
          dbnr_itb_m,
          ddata_itb_m,
          dresp_itb_m,
          dlast_itb_m};

  assign d_boundary_src_valid = dvalid_itb_m;
  assign dready_itb_m = d_boundary_src_ready;

  assign d_data_async = d_boundary_dst_data;
  
  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------
  //  A Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 62
  nic400_ib_tpv_gp_apb4_ib_a_fifo_rd_ysyx_rv32
  u_a_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_m),
     .rclk                  (aclk_m),
     // inputs
     .src_data              (a_data_async),
     .dst_ready             (a_boundary_dst_ready),
     .wpntr_gry_async       (a_wpntr_gry_async),

     // outputs
     .dst_data              (a_boundary_dst_data),
     .dst_valid             (a_boundary_dst_valid),
     .rpntr_gry_async       (a_rpntr_gry_async),
     .rpntr_bin             (a_rpntr_bin)
     );



  //  D Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 40
  nic400_ib_tpv_gp_apb4_ib_d_fifo_wr_ysyx_rv32
  u_d_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_m),
     .wclk                  (aclk_m),
     // inputs
     .src_valid             (d_boundary_src_valid),
     .src_data              (d_boundary_src_data),
     .rpntr_gry_async       (d_rpntr_gry_async),
     .rpntr_bin             (d_rpntr_bin),

     // outputs
     .src_ready             (d_boundary_src_ready),
     .dst_data              (d_boundary_dst_data),
     .wpntr_gry_async       (d_wpntr_gry_async)
     );



  //  W Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 37
  nic400_ib_tpv_gp_apb4_ib_w_fifo_rd_ysyx_rv32
  u_w_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_m),
     .rclk                  (aclk_m),
     // inputs
     .src_data              (w_data_async),
     .dst_ready             (w_boundary_dst_ready),
     .wpntr_gry_async       (w_wpntr_gry_async),

     // outputs
     .dst_data              (w_boundary_dst_data),
     .dst_valid             (w_boundary_dst_valid),
     .rpntr_gry_async       (w_rpntr_gry_async),
     .rpntr_bin             (w_rpntr_bin)
     );




  // ---------------------------------------------------------------------------







endmodule
`include "nic400_ib_tpv_gp_apb4_ib_undefs_ysyx_rv32.v"




// --================================= End ===================================--
